1) Field of the Invention
The present invention relates to a clock distribution circuit which distributes a clock signal to a plurality of cells having clock terminals in a semiconductor integrated circuit in which the plurality of cells are formed on a chip, and more particularly to a clock distribution circuit suitable for use in a semiconductor integrated circuit, such as an LSI, to be incorporated into a multichip module (hereinafter often abbreviated as "MCM").
2) Description of the Related Art
Generally, in the case of a semiconductor integrated circuit, e.g., an LSI, the overall LSI is operated in synchronism with a clock signal or a plurality of clock signals which are out of phase with one another. In such a case, the clock signal received from the outside of the circuit is distributed to flip-flops and the like (cells having clock terminals), in respective parts of the LSI, whereby decoding operations, reading or writing of memory, or various arithmetic operations are performed. If there are differences in length among wiring patterns from the origin of distribution of the clock signal to destinations to which the distributed clock signal is supplied, discrepancies arise in timing at which the clock signals arrive at the destinations (i.e., clock skew arises). If clock skew occurs, there arises a risk that the flip-flop or the like takes in an erroneous signal or that unwanted whisker-like pulses are generated at an output of a logic gate, both resulting in erroneous operation of the circuit. Accordingly, the magnitude of clock skew determines the performance (e.g., an operating speed) of the LSI.
To prevent such clock skew, an H tree clock distribution method such as that shown in FIG. 4 has conventionally been used for a semiconductor integrated circuit, e.g., an LSI. Under the H tree clock distribution method shown in FIG. 4, buffers 101 to 103 are provided in a plurality of stages (three stages are shown in FIG. 4) on a square chip 100, and these buffers 101 to 103 are connected in the form of a tree by means of H-shaoed clock wiring patterns 104 and 105.
More specifically, a first-stage driver 101 for receiving a clock signal from the outside of the chip is disposed at the center of the chip 100. An output from the first-stage driver 101 is input to four second-stage drivers 102 by way of the H-shaped clock wiring pattern 104 centered on the driver 101. The second-stage drivers 102 are provided at the four respective ends of the H-shaped clock wiring pattern 104. The wiring patterns from the first-stage driver 101 to the four second-stage drivers 102 are equal in length.
An output from each of the second-stage drivers 102 is further input to four third-stage drivers 103 by way of an H-shaped clock wiring pattern 105 centered on the corresponding driver 102. The third-stage drivers 103 are provided at the four respective ends of the corresponding H-shaped clock wiring pattern 105. The wiring patterns from the second-stage driver 102 to the corresponding four third-stage drivers 103 are equal in length.
With the drivers 101 to 103 being connected together by way of the clock wiring patterns 104 and 105, the clock signal is supplied to the sixteen third-stage drivers 103 provided at a substantially uniform density within the cell region of the chip 100, and the clock signal is supplied to the clock terminal of the flip-flop or the like from each of the third-stage driver 103. At this time, the wiring patterns from the first-stage driver 101 to the third-stage drivers 103 become substantially equal in length, and the clock skew can be made uniform among the drivers 103 in the final stage. The third-stage drivers 103 may be connected to other drivers by way of other H-shaped clock wiring patterns, thereby further distributing the clock signal.
Incidentally, a clock distribution method such as that shown in FIG. 5 has also been proposed. Under the clock distribution method shown in FIG. 5, buffers 101 to 103 are provided in three stages on a square chip 200. The buffers 101 to 103 are connected together by means of an H-shaped clock wiring pattern 104 and a mesh-shaped wiring pattern 201.
More specifically, the first-stage driver 101 for receiving a clock signal from the outside of the chip is disposed at the center of the chip 200, as in the case of the chip shown in FIG. 4. An output from the first-stage driver 101 is input to four second-stage drivers 102 by way of the H-shaped clock wiring pattern 104 centered on the driver 101. Sixteen third-stage drivers 103 are provided in the cell region of the chip 200 at a substantially uniform density, as in the case of the chip shown in FIG. 4.
All the output terminals of the four second-stage drivers 102 and the input terminals of the sixteen third-stage drivers 103 are connected together by way of the mesh-shaped wiring pattern 201.
The H-shaped clock wiring pattern 104 and the mesh-shaped wiring pattern 201 are respectively formed into different wiring layers. In the example shown in FIG. 5, all the four second-stage drivers 102 and the sixteen third-stage drivers 103 are provided at the nodes of the mesh-shaped wiring pattern 201. The drivers 102 and 103 are not necessarily required to be positioned on the nodes of the mesh-shaped wiring pattern 201, and the drivers may be provided at other locations on the mesh-shaped wiring pattern 201.
Under the clock distribution method shown in FIG. 5, the output terminals of the second-stage drivers 102 are connected to the input terminals of the third-stage drivers 103 by way of the meshed-wiring pattern 201. Accordingly, this clock distribution method enables the clock skew appearing in the drivers 103 in the final stage to be made uniform more thoroughly than by the clock distribution method shown in FIG. 4.
By the way, a wiring pattern whose width is equal to or less than lpm (of the order of sub-microns) must be formed in the chip 100 or 200. In a case where such a narrow wiring pattern is formed from aluminum, the resistance of the wiring pattern becomes considerable high. Further, in a case where a narrow wiring pattern is formed from copper in the same manner as is the aluminum wiring pattern, the resistance R of the wiring pattern will become low. Since there exists a tendency toward a further reduction in the width of a wiring pattern, an increase in the resistance R will pose a serious problem in the future. The capacitance C of the wiring pattern is determined by a gap between the wiring patterns without regard for the material of the wiring pattern. The gap is the same as the width of the wiring pattern, and hence the capacitance C of the wiring pattern will obviously increase in the future.
As mentioned previously, where the mesh-shaped wiring pattern 201 is formed into a narrow width such as that mentioned previously over the entire cell region of the chip, the resistance R of the mesh-shaped wiring pattern 201 is increased. As a result, the waveform of a clock signal is apt to round, which in turn may hinder proper operation of an LSI or the like formed on the chip 200.
To prevent such a problem, it is also conceivable that the resistance R of the wiring pattern can be reduced by simple formation of the mesh-shaped wiring pattern 201 from a material of low resistance R or by a simple increase in width of the mesh-shaped wiring pattern 201 to thereby prevent rounding of the waveform of the clock signal.
In this case, however, the inductance L becomes high, thereby affecting the clock signal and posing a problem of reflection of the clock signal. For example, as shown in FIG. 6, the waveform of the clock signal itself rises without fail, preventing rounding of the waveform. However, as a result of reflection of the signal stemming from an increase in the inductance L, fluctuations appear in the waveform of the clock signal immediately after the leading edge of the pulse or immediately after the trailing edge or the same. As a result, the clock signal becomes considerably unstable, which in turn may hinder proper operation of an LSI or the like formed on the chic 200.